A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces

초록

This paper presents a high-speed single-ended 4-level pulse amplitude modulation (PAM-4) transceiver for next-generation memory interfaces, achieving a data rate of 32Gb/s. The proposed asymmetrically terminated PAM-4 driver is optimized for pseudo open drain (POD) channel configurations and improves signal-to-noise ratio (SNR) with a larger output swing. The dynamic logic-based high-speed 4-to-1 serializer enhances the transmitter output's jitter characteristic by avoiding high-frequency components in the selection signals. The 4-tap feed-forward equalizer (FFE) with two operation modes and one sliding tap flexibly compensates for inter-symbol interference (ISI) of the channel. In the receiver frontend, a continuous-time linear equalizer (CTLE), which utilizes a trans-admittance stage (TAS) and a trans-impedance amplifier (TIA) with an inductive load, provides high-frequency boosting and robust single-to-differential conversion performance through the design techniques of current source gain-boosting and capacitive compensation. The low kickback noise comparators mitigate clock feedthrough and noise coupling during multi-phase PAM-4 sampling and embed the 1-tap PAM-4 decision feedback equalizer (DFE) operation by directly feeding back the previous sampling phase's outputs. The transceiver prototype fabricated in 28-nm CMOS technology occupies 0.126 mm(2). At 32 Gb/s, a bit error rate of under 10(-12) was achieved with a 6.25% eye margin and an energy efficiency of 3.37 pJ/bit while equalizing the 6.87-dB channel loss at 8 GHz.

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