Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN

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초록

In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

키워드

Random access memoryMetalsIterative methodsCircuitsVoltage measurementIntegrated circuit modelingComputer architectureEstimationMicroprocessorsComputational modelingDRAM power integrityhigh-bandwidth memory (HBM)IR-dropon-chip power delivery network (PDN)Computer aided designDynamic random access storageElectric power transmissionIntegrated circuit designLogic designReliability
제목
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN
저자
Hyun, JinhoonJeong, InchulChu, ShinhoLim, Jaemyung
DOI
10.1109/TCAD.2025.3607129
발행일
2026-04
유형
Article
저널명
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
45
4
페이지
1782 ~ 1786