Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN

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초록

In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

키워드

Random access memory; Metals; Iterative methods; Circuits; Voltage measurement; Integrated circuit modeling; Computer architecture; Estimation; Microprocessors; Computational modeling; DRAM power integrity; high-bandwidth memory (HBM); IR-drop; on-chip power delivery network (PDN); Computer aided design; Dynamic random access storage; Electric power transmission; Integrated circuit design; Logic design; Reliability
제목
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN
저자
Hyun, Jinhoon; Jeong, Inchul; Chu, Shinho; Lim, Jaemyung
DOI
10.1109/TCAD.2025.3607129
발행일
2026-04
유형
Article
저널명
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
권
45
호
4
페이지
1782 ~ 1786