Efficient line-based VLSI architecture for 2-D lifting DWT

Wang, Keyan; Wu, Chengke; Liu, Kai; Li, Yunsong; Jeong, Jechang

doi:10.1109/ICIP.2006.312829

상세 보기

Efficient line-based VLSI architecture for 2-D lifting DWT

Wang, Keyan;
Wu, Chengke;
Liu, Kai;
Li, Yunsong;
Jeong, Jechang

Citations

SCOPUS

0

초록

DWT has been the basis of image compression, such as in JPEG2000. This paper proposes a novel VLSI architecture that performs line-based DWT using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. The intermediate buffer is composed of FIFOs to store temporary results of horizontal filters. The control module schedules the output of wavelet coefficients to external memory with the priority from high to low. Horizontal filtering and vertical filtering are simultaneous, and all levels of DWT are processed parallel. The presented architecture finishes multi levels of 9/7 DWT in one image transmission time. Meanwhile, it decreases significantly memory used and hardware resource required. This architecture is suitable for various real-time image/video applications.

키워드

VLSI; Wavelet transforms; Column processors; Control module; External memory; Hardware resources; High-to-low; Horizontal filters; Image transmission time; Intermediate buffers; JPEG 2000; Lifting schemes; Multi-level; Row processors; VLSI; VLSI architectures; Wavelet coefficients; Digital image storage; Discrete wavelet transforms; Image compression; Imaging systems; Computer architecture

제목: Efficient line-based VLSI architecture for 2-D lifting DWT

저자: Wang, Keyan; Wu, Chengke; Liu, Kai; Li, Yunsong; Jeong, Jechang

DOI: 10.1109/ICIP.2006.312829

발행일: 2006-10

유형: Conference Paper

저널명: Proceedings - International Conference on Image Processing, ICIP

페이지: 2129 ~ 2132