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A Low Power Digital Logic Structure for High Resolution and High Frame Rate OLEDoS Micro Displays
- Jeong, Seoyeong;
- Jang, Junhyuk;
- Lee, Kichang;
- Lim, Jaemyung
Citations
SCOPUS
0초록
This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6% compared to the conventional data signal tree structure, enabling a low-power design.
키워드
clock gating; digital logic circuit; display driver; Micro display; OLED-on-silicon; Clock distribution networks; Electric clocks
- 제목
- A Low Power Digital Logic Structure for High Resolution and High Frame Rate OLEDoS Micro Displays
- 저자
- Jeong, Seoyeong; Jang, Junhyuk; Lee, Kichang; Lim, Jaemyung
- 발행일
- 2024-06
- 유형
- Conference paper
- 권
- 55
- 호
- 1
- 페이지
- 1705 ~ 1708