A Sturdy MASH Third-Order Noise-Shaping SAR ADC with Reuse of the SAR ADC

초록

This paper presents a sturdy multi-stage (MASH) noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). In the proposed ADC, the SAR ADC used for the first stage conversion is reused in the second stage, thereby minimizing the necessity for additional hardware. The only added analog component is a dynamic open-loop amplifier which is used to amplify the residue of the first stage. This resulted in a SNDR performance enhancement of over 10 dB in comparison with a single stage noise shaping SAR ADC, without any increase in area and circuit complexity. To realize an aggressive noise transfer function (NTF), the loop filter employs an active integrator, which is implemented as a closed-loop integrator utilizing a cascoded floating inverter amplifier (FIA) for power efficiency. A 28−nm CMOS technology and a 1 V power supply are used in the design of the proposed ADC. The simulation results show that the ADC achieves the SNDR of 84.4 dB and power consumption of 577.48μW when operated with a sampling rate of 80MS/s and oversampling ratio (OSR) of 10 resulting in a Schreier figure-of-merit (FoM) of 182.8 dB.

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