Single-device 1C-XNOR operation in charge-trap memcapacitor crossbar for high-density in-memory computing

초록

High-density and energy-efficient XNOR operations are essential for scalable binarized neural network (BNN) hardware, yet conventional implementations typically require complementary multi-cell configurations, resulting in substantial area overhead. Here, we experimentally demonstrate a single-device 1-capacitor (1 C) XNOR logic scheme utilizing a charge-trap-flash (CTF)-based memcapacitor crossbar array with a NAND flash structure. By exploiting the ambipolar capacitance–voltage characteristics of the memcapacitor, the proposed scheme enables polarity-dependent charge-domain XNOR operations within a single 4 F2 unit cell, eliminating the need for complementary device pairing. A fabricated 48 × 24 memcapacitor array exhibits reliable multistate operation, robust retention exceeding 10 years, and highly linear vector–matrix multiplication under mixed-input conditions with an R2 value of 0.994. The energy per logic operation is experimentally estimated to be as low as 8.4 fJ/μm2 in average, while maintaining near-zero static power consumption due to the absence of DC conduction paths. To validate hardware feasibility, the final binarized layer of a hybrid software-hardware BNN is experimentally implemented using the fabricated array, achieving inference accuracies of 98.0% for MNIST and 86.7% for Fashion-MNIST with only marginal degradation compared to the ideal software baseline. These results establish the proposed 1 C memcapacitor XNOR scheme as a promising approach for ultra-high-density and energy-efficient charge-domain in-memory computing hardware.

키워드