Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications

  • Lee, Inho
  • Hong, Seongmin
  • Ryu, Giha
  • Park, Yongjun
Citations

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3
Citations

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4

초록

Neural networks are widely used in various applications, but general neural network accelerators support only one application at a time. Therefore, information for each application, such as synaptic weights and bias data, must be loaded quickly to use multiple neural network applications. Field-programmable gate array (FPGA)-based implementation has huge performance overhead owing to low data transmission bandwidth. In order to solve this problem, this paper presents an automated FPGA-based multi-neural network accelerator generation framework that can quickly support several applications by storing neural network application data in an on-chip memory inside the FPGA. To do this, we first design a shared custom hardware accelerator that can support rapid changes in multiple target neural network applications. Then, we introduce an automated multi-neural network accelerator generation framework that performs training, weight quantization, and neural accelerator synthesis.

키워드

acceleratorFPGAneural networkAutomationField programmable gate arrays (FPGA)Neural networksParticle acceleratorsCustom hardwaresFirst designsMulti-neural networksMultiple neural networksMultiple targetsNeural network applicationOn chip memorySynaptic weightAcceleration
제목
Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications
저자
Lee, InhoHong, SeongminRyu, GihaPark, Yongjun
DOI
10.1109/TENCON.2018.8650190
발행일
2019-10
유형
Conference Paper
저널명
IEEE Region 10 Annual International Conference, Proceedings/TENCON
2018-October
페이지
2287 ~ 2290