3D Interconnection Using TGVs on Glass Interposer for Vertical 32 Gbps High-Speed Transmission

초록

The increasing demand for high bandwidth die-to-die interconnects in AI and HPC platforms is accelerating the adoption of the advanced 2.5D/3D heterogeneous integration to overcome the scaling and wiring limitations of conventional SoC approaches. Among candidate interposer materials, glass has emerged as a compelling substrate due to its low dielectric loss, excellent dimensional stability, coefficient of thermal expansion (CTE) compatibility, and suitability for large area panel-level processing. In this work, we implement a low loss vertical signal channel on a glass interposer to enable 32 Gbps die-to-die transmission based on the UCIe standard, addressing the long routing path and associated loss penalties inherent to conventional 2.5D architectures. The proposed 3D package leverages through glass via (TGV) to realize a minimized vertical interconnect length and reduced parasitic. We analyzed SI performance through 3D electromagnetic (EM) simulation across routing schemes. The results demonstrate that glass interposer-based 3D integration provides a robust, scalable, and reproducible foundation for next generation chiplet packaging, enabling high-speed die-to-die interconnections with improved channel loss and SI margin.

키워드