Design and Analysis of Efficient Parallel Hardware Prime Generators

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초록

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.

키워드

Performance analysisdigital integrated circuitsprime numberpublic key cryptosysteminformation securityPRIMALITYEXPONENTIATIONTESTS
제목
Design and Analysis of Efficient Parallel Hardware Prime Generators
저자
Kim, Dong KyueChoi, PiljooLee, Mun-KyuPark, Heejin
DOI
10.5573/JSTS.2016.16.5.564
발행일
2016-10
유형
Article
저널명
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
16
5
페이지
564 ~ 581