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초록
DCT is the main performance bottleneck of the HEVC because it has a lot of repeated operations. Performance of the DCT can be improved by executing these repeated operations in parallel. However, memory operations to access the required data limit performance improvements of the parallelization. In this paper, we parallelize the DCT by using the ASIP developed in our previous work and propose an efficient memory data reorganization scheme to achieve further performance improvements of DCT parallelization.
키워드
ASIP; DCT; HEVC; Memory reorganization; Parallelization; Partial butterfly; ASIP; DCT; HEVC; Parallelizations; Partial butterfly
- 제목
- Memory data reorganization for performance improvement of HEVC DCT
- 저자
- Kim, Hyunwoo; Jo, Song Hyun; Hussain, Farhan; Song, Yong Ho
- 발행일
- 2014-01
- 유형
- Conference Paper
- 저널명
- 13th International Conference on Electronics, Information, and Communication, ICEIC 2014 - Proceedings
- 페이지
- 1 ~ 2