Iterative Pseudo-Soft-Reliability-based Majority-Logic Decoding for NAND Flash Memory

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초록

This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms. CCBY

키워드

Complexity theoryDecodingError analysisError correction codesHamming distanceHamming distanceHard decisionIterative decodingIterative hard-reliability-based majority-logic decoding algorithmNAND flash memoryNonbinary low-density parity-check codesPrediction algorithmsReliabilityErrorsFlash memoryHamming distanceMajority logicMemory architectureNAND circuitsTurbo codesDecoding algorithmError rate performanceFlash memory cellLow density parity checkMajority logic decodingNAND flash memoryPerformance degradationThroughput degradationIterative decoding
제목
Iterative Pseudo-Soft-Reliability-based Majority-Logic Decoding for NAND Flash Memory
저자
Park, KBChung, K
DOI
10.1109/ACCESS.2021.3079939
발행일
2021-05
유형
Article in Press
저널명
IEEE Access
9
페이지
74531 ~ 74538