A 11.4-ENOB First-Order Noise-Shaping SAR ADC With PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

초록

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-insensitive closed-loop integrator and data weighted averaging (DWA). The use of cascode floating inverter amplifier (FIA) type dynamic amplifier with high gain enabled an aggressive noise transfer function while minimizing the power consumption associated with the use of active filter. The proposed ADC generates residue with DWA, the use of which was made possible by employing a second large capacitive digital-to-analog converter (CDAC), which operates after the SAR operation is completed. The proposed ADC is designed with a 28-nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 70 dB and power consumption of 238 μW, when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10 resulting in a Schreier figure-of-merit (FoM) of 172.3 dB.

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