Low Power and High Performance Level-up Shifters for Mobile Devices with Multi-V-DD

초록

Reducing power consumption in a processor using multiple supply voltages is commonly adopted in mobile embedded systems. Level shifters are crucial components in such systems to interface two modules operating with different supply voltage levels. In this paper, we propose two low power and high performance level-up shifters called dual step level-up shifter (DSLS) and stacked dual step level-up shifter (SDSLS). DSLS has a dual step buffer structure to improve the speed and the circuit size over conventional level-up shifters as well as power consumption by avoiding contention. SDSLS is proposed to improve DSLS further for low power consumption by utilizing transistor stacking. By selectively using these two level-up shifters according to the difference between high and low supply voltages, delay is reduced by up to 79.0% and power consumption is reduced by up to 50.2%.

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