Energy-efficient hybrid-mode synapse combining high-speed volatile learning and long-term weight retention

초록

This work develops a device-to-system methodology for on-chip learning by examining how a double-gate hybrid-mode synaptic transistor affects neural-network accuracy and energy consumption. The device operates through two mechanisms: band-to-band tunneling, which enables volatile updates at the top gate, and Fowler-Nordheim tunneling, which provides non-volatile charge storage at the bottom gate. TCAD-calibrated simulations capture the transient responses and threshold-voltage shifts of both mechanisms, revealing on/off current ratios above 108, read-current windows of 5 mu A mu m-1, and well-matched conductance nonlinearities in both volatile and non-volatile modes. The conductance-update ranges obtained from the two modes were mapped to a neural-network model to quantify their effect on learning accuracy. Although the physical processes differ, both modes yield nearly identical update ranges and achieve similar MNIST accuracy: 92.87% for the volatile mode and 93.3% for the non-volatile mode. The volatile pathway consumes 5-10 times less energy under the evaluated bias conditions, owing to its lower write voltage and shorter pulses. By linking device behavior to system-level performance, this study shows that volatile operation can support low-power short-term learning, whereas non-volatile operation provides stable long-term memory with no loss of inference accuracy. These results offer a practical foundation for employing single-transistor hybrid synapses in energy-efficient on-chip learning and neuromorphic processors.

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