Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Park, Heechun; Chang, Kyungjoon; Jeong, Jooyeon; Ahn, Jaehoon; Chung, Ki-Seok; KIM, Taewhan

doi:10.1109/ISOCC53507.2021.9614026

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Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Park, Heechun;
Chang, Kyungjoon;
Jeong, Jooyeon;
Ahn, Jaehoon;
Chung, Ki-Seok;
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초록

Design-Technology-co-optimization (DTCO) is essential in deep submicron technologies (e.g., 14nm and below) to co-optimize process technology and design rules and obtain more benefit from advanced node. As the process technology shrinks to deep submicron, the importance of back-end-of-line (BEOL) interconnect in a full chip design drastically grows since its less-Than-micron width brings unexpected critical design rules that requires novel design techniques. In this paper, we provide a comprehensive survey on recent challenging issues and cutting-edge design methodologies for DTCO in deep submicron interconnect technology, which includes: offset assignment for pin accessibility; monolithic 3D integration; middle-of-line (MOL) utilization for routing; BEOL-Aware representative critical path circuit synthesis; and buried power rail (BPR).

키워드

Computer aided design; Three dimensional integrated circuits; Co-optimization; Deep sub-micron; Deep submicron technology; Deep submicrons; Design rules; Design technologies; Interconnect technology; Optimization methodology; Process Technologies; Sub-micron interconnect; Integrated circuit interconnects

제목: Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

저자: Park, Heechun; Chang, Kyungjoon; Jeong, Jooyeon; Ahn, Jaehoon; Chung, Ki-Seok; KIM, Taewhan

DOI: 10.1109/ISOCC53507.2021.9614026

발행일: 2021-11

유형: Proceedings Paper

저널명: 18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021)

페이지: 215 ~ 218