Carrier charging effect of V3Si nanocrystals floating gate memory structure

초록

We fabricated V3Si nanocrystals embedded in SiO2 dielectric layer as a function of post-annealing conditions and characterized their charging effect to apply a nonvolatile memory device. The V3Si thin layer of 5-nm-thickness was deposited on the SiO2 tunneling layer by r.f. sputtering system. To create nanocrystals structure, the post-annealing process in N-2 gas ambient by rapid thermal annealing method was done at temperature ranges from 600 degrees C to 1000 degrees C as a function of annealing times. After the post-annealing at 800 degrees C for 5 s, the spherical shaped V3Si nanocrystals with average diameter of 4 nm were formed. From the nano-floating gate capacitor structure with V3Si nanocrystals, the memory window was measured about 3.4 V when the sweeping voltages applied from -9 V to 9 V and from 9 V to -9 V. This result indicates that V3Si nanocrystals have a strong potential for the nonvolatile memory device.

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