An Inductive Loading Simultaneous Noise and Input Matching Technique with Current Reuse for Low-Power LNA

  • Huynh, Phuoc B. T.
  • Lee, Gyeong-Seok
  • Park, Jun-Young
  • Yun, Tae-Yeoul
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초록

This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11- μm complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of - 5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.

키워드

Logic gatesImpedanceNoiseLoadingResistanceNoise measurementInductorsImpedance matchingCapacitanceTransconductanceCapacitive loading simultaneous noise and input matching (CLSNIM)inductive loading SNIM (ILSNIM)power constrained SNIM (PCSNIM)simultaneous noise and input matching (SNIM)CMOS LNAAMPLIFIEROPTIMIZATIONSUBSTRATEDESIGNFIGUREDBESD
제목
An Inductive Loading Simultaneous Noise and Input Matching Technique with Current Reuse for Low-Power LNA
저자
Huynh, Phuoc B. T.Lee, Gyeong-SeokPark, Jun-YoungYun, Tae-Yeoul
DOI
10.1109/JSSC.2024.3511578
발행일
2025-07
유형
Article in press
저널명
IEEE Journal of Solid-State Circuits
60
7
페이지
2461 ~ 2472