상세 보기
A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees
- Jang, Yooseong;
- Yun, Seokmin;
- Yang, Jeonghyu;
- Shin, Taeho;
- Song, Eunji;
- ... Han, Jaeduk
Citations
SCOPUS
0초록
This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.
키워드
current-mode logic (CML); feed-forward equalizers (FFE); four-level pulse-amplitude modulation (PAM-4); Transmitters; Bias voltage; Computer circuits; Emitter coupled logic circuits; Energy efficiency; Equalizers; Pulse amplitude modulation; Surface mount technology
- 제목
- A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees
- 저자
- Jang, Yooseong; Yun, Seokmin; Yang, Jeonghyu; Shin, Taeho; Song, Eunji; Han, Jaeduk
- 발행일
- 2025-05
- 유형
- Conference paper
- 저널명
- IEEE International Symposium on Circuits and Systems proceedings
- 페이지
- 1 ~ 5
- 언어
- ENG
- 발행국가
- 영국
- 분량
- 5 페이지
- ISSN
- E 2158-1525
P 0271-4302