상세 보기
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
- Wang, Zhongkai;
- Choi, Minsoo;
- Kwon, Paul;
- Lee, Kyoungtae;
- Yin, Bozhi;
- ... Han, Jaeduk;
- 외 5명
Citations
SCOPUS
4초록
This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.
키워드
28nm; CMOS; SerDes; Sub-sampling PLL; Transmitter; CMOS integrated circuits; Phase locked loops; Pulse amplitude modulation; Transmitters; 28nm; 28nm CMOS; CMOS; CMOS technology; Delta-sigma; Modulator clock; Serdes; Sub-sampling; Sub-sampling PLL; Timing control
- 제목
- A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
- 저자
- Wang, Zhongkai; Choi, Minsoo; Kwon, Paul; Lee, Kyoungtae; Yin, Bozhi; Liu, Zhaokai; Park, Kwanseo; Biswas, Ayan; Han, Jaeduk; Du, Sijun; Alon, Elad
- 발행일
- 2022-06
- 유형
- Conference Paper
- 저널명
- Digest of Technical Papers - Symposium on VLSI Technology
- 권
- 2022-June
- 페이지
- 34 ~ 35