An efficient hardware and software co-verification method for HEVC decoders

초록

The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs. Therefore, software and hardware co-verification has emerged as more efficient and desirable methodology. This paper proposes a co-verification method which verifies a system with hardware IPs under a real application execution. In this paper, we show how to verify the functionality of a high efficient video coding (HEVC) decoder with inverse discrete cosine transform (IDCT) hardware IPs using the proposed hardware/software co-verification method. Experimental results show that we can not only efficiently verify the functionality but also analyze circuit size, operation speed and power consumption of the system using the proposed method.

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