HGEN: A Hierarchical Layout Framework for Automated IP Integration

초록

The reuse of pre-verified Intellectual Property (IP) is essential in modern Analog and Mixed-Signal (AMS) design. However, conventional layout automation frameworks are not equipped to integrate this IP directly, often requiring its procedural re-implementation. This paper presents HGEN, a hierarchical layout framework that addresses this challenge through a "place-and-abstract" methodology. HGEN directly utilizes original IP layouts, abstracting their physical data to create a foundation for automation tasks such as placement-aware grid generation and geometry-driven pin access. Interconnects are then completed by a hybrid engine that combines an A* search for pathfinding with manual specifications for critical nets. We validate HGEN’s effectiveness through an industrial Digitally Controlled Delay Line (DCDL) generator, which demonstrates the generator’s portability by producing DRC/LVS clean layouts across multiple process technologies from a single script. The results show that HGEN reduces design cycle time while preserving layout quality and electrical performance.

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