Enhancement of Electrical Characteristics Using a Nanoscale Inserted Gate Structure in FinFET

초록

Variations in the electrical characteristics resulting from the inserted gate structure in the FinFET were investigated by using a technology computer-aided design tool, Sentaurus To solve the inherent problems of the conventional FinFET, a nanoscale gate structure was inserted into the bottom of the FinFET gate. The electrical characteristics of FinFET with the inserted gate structure were significantly affected by the changing depth and thickness of the inserted gate structure. The on-current level and the subthreshold swing of the FinFET with the inserted gate structure were improved in comparison with those of the conventional FinFET due to the shifted maximum current density region in the fin. The electric field of the proposed FinFET was decreased due to the inserted gate structure in comparison with that of the conventional FinFET. This reduction resulted in an increase in the electric density and mobility of the fin for the FinFET with the inserted gate structure. The channel forming region was spread over the entire area by optimizing the depth and thickness of the inserted gate structure. The electrical characteristics of the FinFET containing the inserted gate structure with a depth of 1 nm and a thickness of 2 nm were significantly enhanced in comparison with those of the conventional FinFET.

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