Interface-Engineered TiO2 Interlayer for Reliable Hafnia-Based MFMIS FeFETs

초록

We investigated a TiO2-engineered interfacial strategy to enhance the stability and reliability of hafnia-based ferroelectric field-effect transistors (FeFETs) employing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) architecture. Although the MFMIS configuration facilitates optimized voltage distribution and suppresses charge injection into the dielectric layer, interfacial defects-particularly oxygen vacancies (VOs)-at the floating gate/ferroelectric interface continue to degrade switching performance. To address this issue, we introduced an ultrathin TiO2 interlayer between the floating gate (FG) and the ferroelectric layer. Acting as an oxygen reservoir, the TiO2 interlayer effectively mitigates VO formation and stabilizes the interfacial structure. X-ray photoelectron spectroscopy and electron energy loss spectroscopy analyses confirm a reduced concentration of VO at the interface. Consequently, TiO2-inserted MFMIS devices exhibit enlarged and more stable memory windows, along with enhanced ferroelectric characteristics. Furthermore, low-frequency noise analysis reveals a significant reduction in defect-related fluctuations, indicating suppressed trap dynamics. Collectively, these results demonstrate that TiO2 interface engineering offers a scalable and complementary metal-oxide-semiconductor-compatible strategy to address reliability challenges in hafnia-based ferroelectric transistors.

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