Vertical Channel NAND Flash Structure using DSCG(Double-Side-Control-Gate) to Reduce Cell to Cell Interference

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초록

In this study we proposed the 'Double-Side- Control-Gate'(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the reduction of interference effect. To demonstrate the performance improvement of the proposed architecture, we analyzed cell-to-cell interference in 3-bit multi-cells and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared and estimated benefits expected from the application of DSCG by calculating Cell-to-Cell Distance(CTCD), pass voltage, etc. Lastly, we confirmed the above 90% reduction of the Cell-to-Cell interference using the DSCG structure.

키워드

Vertical channelDSCGpolysilicon3-D memory3-D block3-D stacked NAND Flash memorythin film
제목
Vertical Channel NAND Flash Structure using DSCG(Double-Side-Control-Gate) to Reduce Cell to Cell Interference
저자
Choi, SeonjunSong, Yun Heub
DOI
10.5573/JSTS.2018.18.6.714
발행일
2018-12
유형
Article
저널명
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
18
6
페이지
714 ~ 722