Timing driven force-directed floorplanning with incremental static timing analyzer

초록

As nano-scale technology is widely adopted, minimizing the interconnection delay has become one of the most critical issues in designing high performance systems. To achieve fast timing closure, it is very important to estimate the interconnection delay accurately at an early design stage. In this paper, we propose a novel timing driven force-directed floorplanning technique using an efficient incremental static timing analyzer. Our proposed floorplan framework contains a fast and accurate interconnection delay estimator which is very important to obtain an excellent floorplan. The proposed timing methodology has been implemented as a part of a commercial floorplanning tool called Pillar-DP from Entasys Design Inc. We carried out experiments on several benchmarks to show the effectiveness of our approach. The experiment results show that our tool is valuable in generating a near optimal floorplan within a reasonable amount of time.

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