Bayesian spatial defect pattern recognition in semiconductor fabrication using support vector clustering

초록

Defects generated during integrated circuit (IC) fabrication processes are classified into global defects and local defects according to their generation causes. Spatial patterns of locally clustered defects are likely to contain the information related to their defect generation mechanisms. In this paper, we propose a model-based clustering for spatial patterns of local defects to reflect real situations. A flexible two-step approach is proposed to classify the spatial defects patterns via support vector clustering and Bayesian method. Support vector clustering is employed to separate global defects from the local ones to improve both clustering accuracy and computational efficiency in further analysis. A new mixture model is proposed for modeling the distribution of local defects on the wafers. Local defect clusters with amorphous/linear, curvilinear, and ring patterns are modeled by multivariate normal distribution, principal curve, and spherical shell, respectively. A Bayesian inference procedure is then applied for parametric pattern recognition of the local defects. Results from both simulated data and real wafer map data demonstrate potential in applying our approach to analyze general defect patterns in IC manufacturing.

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