Fully Programmable Redundancy Circuits for STT-MRAM

초록

We propose fully programmable redundancy schemes for spin-transfer-torque magnetic random access memories (STT-MRAMs). To store redundancy information, these schemes use magnetic tunnel junctions (MTJs), which are core memory elements of STT-MRAMs. This can greatly simplify the fabrication process of STT-MRAMs. Furthermore, it also allows reprogramming of the redundancy information after packaging or even during normal use by end-users without requiring any special high-voltage setup. We propose two redundancy schemes. First, we propose an address comparator, which uses MTJs and is a direct replacement of a conventional address comparator. Second, we propose a scheme in which the redundancy circuits share the storage cells and read-write peripheral circuits with the normal data array structure.

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