Stabilized negative capacitance for near-theoretical efficiency and high reliability in charge trap flash memory

초록

Negative capacitance (NC) in ferroelectric heterostructures offers a promising pathway to internal voltage application for energy-efficient electronics. However, its adoption in non-volatile memory has been hindered by instability and limited endurance. Here, we demonstrate a stabilized NC-enhanced charge trap flash (NC-CTF) memory that simultaneously achieves high programming efficiency, long retention, and robust cycling endurance through dual interfacial engineering. An ultrathin Al2O3 interlayer in Hf0.5Zr0.5O2 (HZO) modulates domain configurations and promotes energy redistribution into depolarization energy, reinforcing the NC effect. Simultaneously, a TiO2 layer between the charge trap layer (CTL) and blocking oxide (BO) increases the conduction band offset, suppressing parasitic charge injection and degradation. As a result, the NC-CTF device achieves a near-ideal incremental step pulse programming (ISPP) slope of similar to 0.95, a 13.4 V memory window enabling quad-level cell (QLC) operation, and endurance exceeding 10(4) program/erase cycles. The integration of NC physics with flash memory architecture offers a scalable and CMOS-compatible platform for ultra-low-power memory and neuromorphic computing, contributing to the advancement of energy-efficient and intelligent nano-electronic systems.

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