An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

  • Wang, Zhongkai
  • Choi, Minsoo
  • Lee, Kyoungtae
  • Park, Kwanseo
  • Liu, Zhaokai
  • ... Han, Jaeduk
  • 외 3명
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초록

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

키워드

28 nm4:1 multiplexer (MUX)BandwidthBerkeley Analog Generator (BAG)clock distributionClocksComputer architecturefour-level pulse-amplitude modulation (PAM-4)GeneratorsOptical signal processingPulse generationpulse generatorquarter-rateSerDestransmitter (TX)Voltagewireline.BandwidthCapacitanceCMOS integrated circuitsFlexible electronicsTransmitters4:1 multiplexerCMOS technologyCurrent sourcesFeedforward equalizerNon-return to zerosReconfigurableTarget data rateTransmitters (Tx)Pulse amplitude modulation
제목
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS
저자
Wang, ZhongkaiChoi, MinsooLee, KyoungtaePark, KwanseoLiu, ZhaokaiBiswas, AyanHan, JaedukDu, SijunAlon, Elad
DOI
10.1109/JSSC.2021.3109562
발행일
2021-09
유형
Article; Early Access
저널명
IEEE Journal of Solid-State Circuits
57
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