A 6.0 TOPS/W Reconfigurable AI-Based Channel State Information Compression Using Delta Encoding in Multi-Receiver Mobile Systems

초록

This paper presents a low-power processor for AI-based channel state information (CSI) compression, for the first time. Exploiting the high similarity between signals from multiple receivers, the proposed delta encoding enhances sparsity and generates small-magnitude numbers, reducing energy consumption in computation and data movement. A customized computing paradigm, integrating mixed sign-magnitude (S&M) and two's complement (2S/C) number representations, is developed to further optimize efficiency. The architecture also offers high reconfigurability, supporting diverse layer structures in state-of-the-art models for CSI compression, including hybrid convolution (CONV) and transformer blocks. Fabricated using a 65 nm process, the silicon prototype achieves a peak energy efficiency of 6.0TOPS/W, highlighting its potential for mobile devices.

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