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초록
Parallel processing techniques are increasingly found in reconfigurable computing, especially in digital signal processing (DSP) applications. In this paper, we design a parallel reconfigurable computing (PRC) architecture which consists of multiple dynamically reconfigurable computing units. The hidden Markov model (HMM) algorithm is mapped onto the PRC architecture. First, we construct a directed acyclic graph (DAG) to represent the HMM algorithms. A novel parallel partition approach is then proposed to map the HMM DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different HHM states.
키워드
FPGA; HMM; parallel processors; partitioning algorithm; reconfigurable processing; FPGA; HMM; Parallel processor; Partitioning algorithms; Reconfigurable processing; Algorithms; Axial flow; Computation theory; Hidden Markov models; Optimization; Reconfigurable hardware; Signal processing; Structural design; Parallel processing systems
- 제목
- Parallel reconfigurable computing and its application to hidden Markov model
- 저자
- Paul, Anand; Jiang, , Yung-Chuan; Jeong, Jechang
- 발행일
- 2010-11
- 유형
- Conference Paper
- 저널명
- IET Conference Publications
- 권
- 2010
- 호
- 568 CP
- 페이지
- 82 ~ 91