A Fast-Locking PLL Using Low-Power Cycle Slippage Compensation and Accumulated Phase Error Correction

초록

This article presents a fast-locking phase-locked loop (PLL) that incorporates a low-power extended phase frequency detector (LPEPFD) and a discriminator-aided phase detector (DAPD) to simultaneously address cycle slippage and frequency overshoot issues during frequency and phase acquisition, respectively. Specifically, the proposed LPEPFD introduces a novel finite state machine architecture that extends the linear range of a conventional PFD without requiring a power-hungry counter, thereby eliminating cycle slippage and reducing the time required for frequency acquisition while maintaining switching activity and power consumption comparable to those of the conventional design. Moreover, after frequency convergence, the DAPD quantizes the accumulated phase error, which is corrected by adaptively tuning the programmable delay lines without causing significant frequency overshoot seen in conventional PLLs, resulting in improved settling time. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the proposed fast-locking PLL occupies an area of 0.36 mm2 and operates over a frequency range of 2.6 to 3.2 GHz. Experimental results demonstrate a 0.84-μs settling time for a frequency hop from 2.6 to 3.1 GHz. The designed PLL consumes 5.6 mW of power from a supply of 1 V with an integral root-mean-square jitter of 1.27 ps from 1 kHz to 100 MHz.

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