Interlayer and Band-Engineered Charge Trap Flash Enabling Low Voltage and Reliable Quad Level Operation

초록

Developing charge-trap flash that can operate reliably at low voltages while supporting quad-level storage requires both controlled charge placement and stable switching behavior throughout repeated cycling. In this study, we introduce a device architecture that combines a thin interfacial layer inside the HfZrOx stack with a charge-trap layer designed to reshape its energy-band profile. Measurements confirm that inserting the interlayer alters the internal polarization response of the dielectric, yielding a broader programmable window, lower program and erase thresholds, and improved step-wise programming characteristics. The modified charge-trap layer further contributes to stable performance by restricting excessive electron injection, resulting in more uniform program and erase transitions even after extended cycling. Collectively, these engineering approaches enable a memory window of 13.6 V, strong incremental programming efficiency, robust disturb immunity, and sustained quad-level storage. A qualitative interpretation based on switching-energy considerations suggests that the interlayer helps maintain a more uniform polarization evolution, while the engineered trap layer reduces interface-driven variation, supporting a dependable platform for future low-voltage quad-level flash technologies

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