양자내성암호 알고리즘 NTRU의 저면적 하드웨어 IP 개발

초록

This paper proposes an implementation of lightweight PQC algorithm NTRU hardware. The architecture is designed to do some part of arithmetic operation while printing out 32-bit data, which leads to reduce the number of copies of some submodules from 821 to 16. We also saved registers and multiplexers by reusing register space and saving data at proper position. As a result, proposed NTRU hardware occupied only G.E. 413,938, which is 29% reduced area compared to the previous paper[1].