Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC

초록

As modern hardware architectures are complicated, designing hardware systems is challenging. High level synthesis (HLS) has emerged as an effective hardware synthesis method that saves the engineering cost and the design time. Meanwhile, field programmable gate array (FPGA) devices have been improved significantly in terms of both performance and power efficiency, and therefore, they are often considered as an alternative hardware implementation to application specific integrated circuits (ASICs). SDSoC is a C/C++ development environment which enables developers to leverage both configurable hardware and software implementations. This paper introduces a hardware-software co-design of low density parity check (LDPC) decoding synthesized by SDSoC for a heterogeneous FPGA and central processing unit (CPU) platform. The LDPC code is one of the strongest error correcting codes. In order to optimize performance, the LDPC decoding process is divided into several stages. Then, either software or FPGA implementation is selected based on algorithmic characteristics and data dependencies of each stage. For stages which are implemented on the FPGA device, loop unrolling and loop pipelining techniques are applied. Compared to a pure software decoder, the proposed LDPC decoder achieved a speed-up of 4.41 while maintaining the software decoder's BER performance and flexibility for various standards

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