High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology

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초록

This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-To-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch-based bang-bang PD has a smaller clock-To-Q delay and a higher data rate.

키워드

clock-To-Q delayphase detectorpower consumptionStorngARM latch
제목
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology
저자
Sung, GaeryunHan, Jae duk
DOI
10.1109/ISOCC53507.2021.9613931
발행일
2021-11
유형
Proceedings Paper
저널명
18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021)
페이지
377 ~ 378