Crater-free through-silicon vias formation by hybrid multi-step femtosecond laser drilling: Surface morphology control and residual stress reduction

초록

Through-silicon vias are a key technology in advanced semiconductor packaging to enable high-performance computing applications. Femtosecond laser drilling provides faster processing speed and selective modification compared to conventional dry etching. However, the high pulse energy of the single mode generates rapid plasma expansion, resulting in high residual stress, rough cross-sections, and a low aspect ratio. In contrast, the burst mode, which irradiates low-energy sub-pulses at narrow intervals, produces large surface craters and a wide heat-affected zone owing to the heat accumulation effect. These defects generated by conventional femtosecond laser drilling degrade the overall performance of through-silicon vias. To overcome these limitations, this study proposes a novel hybrid multi-step femtosecond laser drilling process. The proposed process consists of three steps: Step 1 involves guide hole formation using single mode, which provides a plasma expansion path to suppress residual stress generation. Step 2 conducts via hole drilling using burst mode. The guide hole in Step 1 mitigates heat accumulation during this step, which results in a reduction of the heataffected zone and surface craters. Step 3 focuses on crater trimming using single mode. By designing the ablation diameter according to the laser fluence, the residual craters are effectively removed. This process demonstrates that crater trimming can be achieved solely through laser processing. Experimental results show that the proposed process increased the aspect ratio by approximately 1.7 times, achieved a taper angle of 0.25 degrees at a depth of 100 mu m, and produced crater-free via holes. In addition, it improved sidewall roughness (Rq) by approximately 59.3 %, reduced the residual stress by approximately 34.2 %. The proposed process improved via hole quality using solely laser processing technology and validated its applicability for high-density semiconductor packaging.

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