A 154-mu W 80-dB SNDR analog-to-digital front-end for digital hearing aids

초록

A low-power, low-noise analog-to-digital frontend for digital hearing aids consisting of a preamplifier and a delta-sigma (DS) ADC with a decimation filter is presented. The high-input-impedance preamplifier has a variable gain from 14 to 23 dB. The power consumption of the preamplifier is kept low by employing operational amplifiers with class-AB output and a capacitive anti-aliasing filter. The DS modulator employs a 4th order feed-forward topology with 6-level quantization to reduce the power consumption and distortion. The designed front-end has been implemented using a 130 nm CMOS process and achieved 82.1 dB SNR and 80.1 dB SNDR over a 7.5 kHz signal band, which satisfies the requirement for digital hearing aids. The total chip dissipates a power of 154 mu W from a 1.2 V supply.

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