The Opportunity of Anti-ferroelectrics in FeFET for Emerging Non-Volatile Memory Applications

초록

We demonstrate a novel Ferroelectric FET (FeFET) configuration designed to expand memory window (MW) and enhance retention via two approaches: (i) the introduction of a charge trap layer (CTL) and (ii). the adoption of anti-ferroelectric (AFE) material. The retention loss in metal-interlayer (IL)-ferroelectric (FE)-IL-silicon (MIFIS) FeFET is ascribed to the negative feedback loop, involving the de-trap of interface trap charge from gate (Qit') and the loss of polarization (P) which mutually accelerates the further loss of the other. Our first approach, CTL on top of FE, provides additional trap sites with deep trap levels which introduces favorable charge (QN) with high stability, thus enhancing both MW and retention. Moreover, by utilizing the high spontaneous polarization (Ps) and low remanent polarization (Pr) nature of AFE, we further improved the retention characteristics by increasing the proportion of QN and decoupling the negative feedback loop. By proposing a new FeFET design with a high MW (12.9 V), a low operation voltage (+17/-14 V), and enhanced data retention, we suggest that the hafnia-based FeFET can be a big step forward for 3D NAND technology.

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