다중화된 곱셈기를 이용한 델타-시그마 AD 컨버터용 디지털 데시메이션 필터

초록

A hardware-effective digital decimation filter implementation used in a 16-bit delta-sigma A/D converter for audio application is described. The digital decimation filter uses multi-stage multi-rate signal processing to relax the filter design. Since the multipliers are the most hardware consuming components in digital filters, we optimized multiplier usage. This implementation is well suited for VLSI and can be applied to many other high resolution delta-sigma ADC.