초 저전력 CMOS 2.4 GHz 저잡음 증폭기 설계

초록

In this paper, we proposed an ultra-low power low noise amplifier(LNA) using a TSMC 0.18 μm RF CMOS process. To satisfy the low power consumption with high gain, a current-reused technique is utilized. In addition, a low bias voltage in the subthreshold region is utilized to achieve ultra low power characteristic. The designed LNA has the voltage gain of 13.8 dB and noise figure(NF) of 3.4 dB at 2.4 GHz. The total power consumption of the designed LNA is only 0.63 mW from 0.9 V supply voltage and chip occupies 1.1 mm×0.8 mm area.

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