상세 보기
Low-power counter for column-parallel CMOS image sensors
- Kim, Jong-Seok;
- Yoon, Jin-O;
- Choi, Byong-Deok
Citations
SCOPUS
13초록
A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.
키워드
CMOS image sensor (CIS); column-parallel ADC; correlated double sampling (CDS); counter; Digital cameras; Flip flop circuits; Image sensors; Pixels; Clock signal; CMOS image sensor; Cmos image sensor (CISs); Column parallel; Correlated double sampling; counter; D flip flops; Low Power; CMOS integrated circuits
- 제목
- Low-power counter for column-parallel CMOS image sensors
- 저자
- Kim, Jong-Seok; Yoon, Jin-O; Choi, Byong-Deok
- 발행일
- 2017-01
- 유형
- Conference Paper
- 저널명
- 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
- 페이지
- 554 ~ 556
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- 발행국가
- 미국
- 분량
- 3 페이지
- ISSN
- P 0000-0000