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An ASIP approach for interpolation performance enhancement in HEVC decoder
- Lee, Minkyu;
- Song, Yong Ho;
- Chung, Ki-Seok
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0초록
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC-D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica processor using Tensilica instruction extension (TIE).
키워드
ASIP; HEVC; interpolation; motion compensation; Application specific integrated circuits; Decoding; Image compression; Interpolation; Microprocessor chips; Motion analysis; Motion compensation; Video signal processing; Application specific instruction set processor; ASIP; Compression efficiency; HEVC; High-efficiency video coding; Instruction set architecture; Performance enhancements; Video compression standards; Computer architecture
- 제목
- An ASIP approach for interpolation performance enhancement in HEVC decoder
- 저자
- Lee, Minkyu; Song, Yong Ho; Chung, Ki-Seok
- 발행일
- 2014-09
- 유형
- Conference Paper
- 저널명
- Proceedings of 2014 4th IEEE International Conference on Network Infrastructure and Digital Content, IEEE IC-NIDC 2014
- 페이지
- 232 ~ 235
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- 발행국가
- 대한민국
- 분량
- 4 페이지
- ISSN
- P 0000-0000