Optimization of FPGA-based LDPC decoder using high-level synthesis

초록

Low Density Parity Check (LDPC) codes are widely used in various communication and storage systems due to outstanding error correcting capability. In this paper, we present a Field Programmable Gate Array (FPGA) implementation of the LDPC decoder using High-Level Synthesis (HLS). Because HLS can synthesize a hardware implementation from a high-level description, it is very effective in reducing design time, and in exploring various design alternatives. One of the biggest advantages of FPGAs is flexibility, and therefore, HLS for FPGAs is widely adopted as a good hardware synthesis method. In this paper, we describe an LDPC decoder in high level language, and a HLS tool called SDSoC is used to synthesize the decoder. The proposed design is a serial LDPC decoder that requires smaller amount on hardware resource and power consumption than the conventional design. The major drawback of a serial decoder is slow speed. To overcome such drawback, optimization techniques such as array partitioning, loop unrolling, pipelining methods and fixed-point conversion are applied. With the application of these techniques, the decoding speed of the proposed implementation is 8.11 times and 2.79 times faster than that of a non-optimized implementation and that of a software-based LDPC decoder, respectively.

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