Reconfigurable Spike Routing Architectures for On-Chip Local Learning in Neuromorphic Systems

초록

Lookup table (LUT)-based spike routing schemes are often used in inference-only neuromorphic systems for their excellent reconfigurability. Yet, the routing in such schemes leaves difficulty in on-chip learning following a local learning rule, which requires a number of synaptic updates upon each spike. In this work, this issue is addressed by investigating four LUT-based routing schemes that use different LUT read-out techniques for on-chip learning. They are random access memory (RAM), content addressable memory, partitioned RAM, and pointer (PTR)-based routing schemes. A theoretical means of evaluating the maximum network size for each scheme without routing congestion-experimentally justified using field-programmable gate array implementations-is first provided. The results indicate that the PTR-based scheme supports a neuromorphic core consisting of 20 000 neurons (simultaneously firing at 50 Hz) and 2 million synapses at 200 MHz clock speed with minimum circuit overhead. The PTR-based scheme is further applied to multiple cores in a large-scale neuromorphic cluster, revealing that the cluster can theoretically hold 1.81 million neurons (simultaneously firing at 50 Hz) and 362 million synapses at 100 MHz global clock speed (separate clock for global event routing) when all cores operate at 200 MHz local clock speed (clock for local event routing).

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