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A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology
- Jo, Yunseong;
- Kang, Taeseung;
- Yang, Jeonghyu;
- Han, Jaeduk
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0초록
This paper presents the process of generating the layout of the 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). By utilizing LAYGO2 [1], a Python framework that allows for detailed and flexible specification of custom layout generation processes, code-based generators for the component blocks of a SAR ADC were developed according to their specific operational characteristics and requirements. As a result, 85.5% of the SAR ADC was automatically generated. The SAR ADC test chip was fabricated in a 14-nm CMOS FinFET process and achieved an SNDR of 41.67 dB at 500 MS/s, consuming 2.07 mW from 0.9 V supply, and occupying an area of 4,131 um2
키워드
FinFET; LAYGO2; layout generation; SAR ADC; CMOS integrated circuits; Digital to analog conversion; Integrated circuit layout; Phase locked loops; Problem oriented languages
- 제목
- A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology
- 저자
- Jo, Yunseong; Kang, Taeseung; Yang, Jeonghyu; Han, Jaeduk
- 발행일
- 2025-03
- 유형
- Proceedings Paper
- 저널명
- 30TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2025
- 페이지
- 338 ~ 341