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A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS
- Lee, Sangwan;
- Seo, Hyeongmin;
- Son, Seungwoo;
- Yeom, Sunoh;
- Han, Jaeduk
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6초록
This brief proposes a 102-Gb/s eight-level pulse amplitude modulation (PAM-8) wireline receiver frontend system with high linearity. The receiver adopts a strategy wherein the differential signal undergoes division in the analog domain before equalization. The bias shifters control the common-mode voltage of the input signal to provide distinct dynamic regions for multiple equalizer pathways. The bias shifter circuits employing passive devices ensure both power saving and full linearity. The proposed PAM-8 receiver frontend operates at 102 Gb/s with an efficiency of 1.61 pJ/b and a linear input range of 1.4-Vppd in 28-nm CMOS.
키워드
bias shifter; Circuits; continuous-time linear equalizer; Equalizers; high-swing signaling; Linearity; linearity; nonlinear compression; PAM-8; Power demand; Receivers; Signal to noise ratio; Voltage; Bias voltage; CMOS integrated circuits; Continuous time systems; Pulse amplitude modulation; Signal receivers; Signal to noise ratio; Timing circuits
- 제목
- A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS
- 저자
- Lee, Sangwan; Seo, Hyeongmin; Son, Seungwoo; Yeom, Sunoh; Han, Jaeduk
- 발행일
- 2024-11
- 유형
- Article
- 권
- 71
- 호
- 11
- 페이지
- 4623 ~ 4627