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초록
In this paper, a implementation of the I/Q signal combining for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader receiver is presented. The design is concentrated on the low complexity and the low coast of the RFID reader. To reduce the complexity, area consumption and calculation time, the Loop Up Table (LUT) is applied. Only one multiplier and one divider which have many gates size is used for the low cost. The FPGA NCsim simulator is used to verify this design and it is tested on the reader platform based on FPGA. The simulation, design results and the performance results of the reader receiver using the I/Q signal combining is presented.
키워드
FPGA; I/Q signal combining; RFID; Calculation time; FPGA; FPGA design; I/Q signal combining; Low complexity; Low costs; Radio-frequency identification readers; RFID; RFID readers; UHF RFID reader; Ultra-high frequency; Design; Field programmable gate arrays (FPGA); Radio frequency identification (RFID); Signal receivers
- 제목
- A FPGA design of the I/Q signal combining for UHF RFID reader receiver
- 저자
- Kim, Sang Kyu; Nam, Sung Sik; Cho, Sung Ho
- 발행일
- 2010-12
- 유형
- Conference Paper
- 저널명
- Proceedings - 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content, IC-NIDC 2010
- 페이지
- 556 ~ 560