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8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
- Choi, M.;
- Wang, Z.;
- Lee, K.;
- Park, K.;
- Liu, Z.;
- ... Han, J.;
- 외 2명
초록
The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture. © 2021 IEEE.
- 제목
- 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
- 저자
- Choi, M.; Wang, Z.; Lee, K.; Park, K.; Liu, Z.; Biswas, A.; Han, J.; Alon, E.
- 발행일
- 2021-02-13
- 학회명
- 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
- 개최국가
- 미국
- 학회 개최일
- 2021-02-13 ~ 2021-02-22