Mitigating Row-hammering by Adapting the Probability of Additional Row Refresh

초록

Continuous scaling-down of the DRAM manufacturing process technology has achieved a dense chip capacity with a low cost-per-bit. On the other hand, it has introduced a new reliability problem called row-hammering, in which, in case that a certain row is activated too frequently, one or more bits in the adjacent rows are unintentionally corrupted. It is crucial to address row-hammering errors because they not only can be exploited by a malicious attack for modern computing systems but also may occur in general applications stored in a highly scaled-down DRAM. Even if several methods have been proposed to resolve row-hammering, existing solutions have limited capability to prevent row-hammering from occurring. Hence, a more robust solution for row-hammering is necessary. In this paper, we propose a novel row-hammering mitigation mechanism, called Adaptive-probabilistic Additional Row Refresh (AARR). The main observation exploited by the proposed method is that each memory access does not have an equal degree of threat to cause row-hammering: accessing a row that has been frequently activated is much vulnerable to row-hammering rather than a barely activated row. In AARR, a small table and a few logic blocks are added to keep track of the threat level that causes row-hammering. Then, one of the adjacent rows of an accessed row is refreshed with an adaptive probability that corresponds to the threat level of that memory access. Our evaluation results show that the proposed method renders the most reliable protection against row-hammering with the lowest overhead on performance and energy compared to two well-known existing solutions.

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